1. Field of the Invention
This invention relates to computers and data processing systems which include apparatus and methods for preventing skew between the initial pulses of a train of clock pulses from adversely effecting the operation of circuits dependent upon such clock pulses. The present invention is directed to apparatus and methods for introducing a train of clock pulses to functional circuitry with minimal or no skew between the pulses produced immediately after start up of a master clock or oscillator. More particularly, the present invention relates to methods and apparatus for removing skew from the initial sequence of clock pulses in a train of clock pulses generated by a master clock. This invention is especially useful in an environment of a computer system employing multiple processors which are concurrently operable and require close coordination of their data processing functions with each other.
2. Description of the Prior Art
Multiprocessor computer systems are dependent upon arrival of system clock pulses from a master clock at the utilization circuits with a minimum of variation in timing between pulses and with reliably consistent clock pulse quality. There are two forms of skew between clock pulses which create problems with the system operation. This includes skew between pulses within the train of clock pulses, and skew between the time of arrival of a given clock pulse at a plurality of utilization circuits. The present invention is primarily concerned with the former skew.
Whenever a system clock is first started, the initial pulses of the train it produces are skewed with respect to the subsequent pulses of the train the clock generates. For those initial pulses, the length and the period are far from that of the characteristic steady state clock pulse train which follow. This skew improves for each succeeding clock after the first pulse, or pulses, until steady state is reached. In the past, this problem was addressed either by never turning the clocks off, or by trying to account for the skew in the test results. The former suffers the disadvantage of a loss of testing capability, or flexibility, while the latter has proven marginally successful at best.
It is a well-known technique in the test of digital computer systems and test equipment to n-step through the system, or stop and start the master system clock to allow step by step analysis of performance. Such test circuits sometimes are arranged to start the system clock, and allow a single clock pulse to pass to the utilization circuitry. Thus, the test circuits are not affected by the fact that the first clock produced when the clock is turned on is usually badly skewed relative to the following pulses of the clock pulse train generated thereafter.
Various approaches have addressed the skew associated with pulses arriving at a plurality of utilization circuits. For instance, U.S. Pat. No. 4,675,562 by Herlein et al discusses a test system to aid in synchronizing and deskewing circuits by employing a series of delay circuits to apply predetermined delay to clock signals. It would not solve the problems associated with the skew associated with the initial clock start-up as described here, however, because when the delayed first clock arrives at a test point it is still skewed relative to its successor pulses.
U.S. Pat. No. 5,008,636 by Markinson et al employs a phase-locked loop on each board to maintain synchronization, and compensate for skew developing between clock pulses on different boards. It would not rid the system of the skew in the first few clock pulses generated, however.
No one has successfully resolved the problem of clock skew associated with a master clock, such as are used in computer systems when that clock is stopped and started.